
84
8008H–AVR–04/11
ATtiny48/88
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
11.7
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
Figure 11-5 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes.
Figure 11-5. Timer/Counter Timing Diagram, no Prescaling
Figure 11-6 shows the same timing data, but with the prescaler enabled.
Figure 11-6. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O/8)
Figure 11-7 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode.
clk
Tn
(clk
I/O/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)